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19-4971; Rev 1; 2/10
TION KIT EVALUA BLE ILA AVA
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
General Description
The MAX8893A/MAX8893B/MAX8893C power-management integrated circuits (PMICs) are designed for a variety of portable devices including cellular handsets. The PMICs include a high-efficiency step-down DC-DC converter, five low-dropout linear regulators (LDOs) with programmable output voltages, individual power-on/ off control inputs, a load switch, and a USB high-speed switch. These devices maintain high efficiency with a low no-load supply current, and the small 3.0mm x 2.5mm WLP package makes them ideal for portable devices. The step-down DC-DC converter utilizes a proprietary 4MHz hysteretic PWM control scheme that allows for ultra-small external components. Internal synchronous rectification improves efficiency and eliminates the external Schottky diode that is required in conventional stepdown converters. Its output voltage is programmable by the I2C serial interface and output current is guaranteed up to 500mA. LDO1, LDO4, and LDO5 offer low 45FVRMS output noise and low dropout of only 100mV at 100mA. They deliver up to 300mA, 150mA, and 200mA continuous output currents, respectively. LDO2 and LDO3 each deliver 300mA continuous output current with very low ground current. All LDO output voltages are programmable by the I2C serial interface. Three standard versions of the PMIC are available with different LDO default startup voltages (see Table 1). The MAX8893A/MAX8893B/MAX8893C are available in a 3.0mm x 2.5mm, 30-bump WLP package.
Features
S High-Efficiency Step-Down Converter Guaranteed 500mA Output Current Up to 4MHz Switching Frequency Programmable Output Voltage from 0.8V to 2.4V Dynamic Voltage Scaling with Programmable Ramp Rate S Three Low-Noise LDOs with Programmable Output Voltages S Two Low Supply Current LDOs with Programmable Output Voltages S Low On-Resistance Load Switch S USB High-Speed Switch with 15kV ESD S Individual Enable Control for All Regulators and Switches S I2C Serial Interface S Overcurrent and Thermal Protection for All LDOs S 3.0mm x 2.5mm x 0.64mm, 30-Bump WLP
MAX8893A/MAX8893B/MAX8893C
Ordering Information
PART MAX8893AEWV+ MAX8893BEWV+ MAX8893CEWV+ TEMP RANGE -40NC to +85NC -40NC to +85NC -40NC to +85NC PIN-PACKAGE 30-Bump WLP (3.0mm x 2.5mm) 30-Bump WLP (3.0mm x 2.5mm) 30-Bump WLP (3.0mm x 2.5mm)
Applications
Cellular Handsets Smartphones and PDAs
+Denotes a lead(Pb)-free/RoHS-compliant package.
Typical Operating Circuit appears at end of data sheet.
_______________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
ABSOLUTE MAXIMUM RATINGS
IN1, IN2, BATT, COM1, COM2 to AGND .............-0.3V to +6.0V BUCK, LS, ENLS, ENBUCK, ENLDO1, ENLDO2, ENLDO3, ENLDO45, REFBP, LDO2, LDO3, SCL, SDA, ENUSB, CB, NC1, NC2, NO1, NO2 to AGND .......................... -0.3V to (VBATT + 0.3V) LDO1, LDO4, LDO5 to AGND.................. -0.3V to (VIN2 + 0.3V) PGND to AGND ....................................................-0.3V to +0.3V LX Current ..................................................................... 1.5ARMS LX to AGND (Note 1)................................ -0.3V to (VIN1 + 0.3V) Continuous Power Dissipation (TA = +70NC) 30-Bump, 3.0mm x 2.5mm WLP (derate 20.0mW/NC above +70NC).............................................................1600mW Junction-to-Ambient Thermal Resistance (JA) (Note 2) ........................................................................50NC/W Operating Temperature Range .......................... -40NC to +85NC Junction Temperature .....................................................+150NC Storage Temperature Range............................ -65NC to +150NC Bump Temperature (soldering) Infrared (15s) ...............................................................+200NC Vapor Phase (20s) .......................................................+215NC
Note 1: LX has internal clap diodes to PGND and IN1. Applications that forward bias these diodes should take care not to exceed the IC's package-dissipation limits. Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Notes 3, 4) PARAMETER Input Supply Range Shutdown Supply Current No-Load Supply Current Light-Load Supply Current UNDERVOLTAGE LOCKOUT Undervoltage Lockout (Note 5) THERMAL SHUTDOWN Thermal Shutdown Threshold Thermal Shutdown Hysteresis REFERENCE Reference Bypass Output Voltage REF Supply Rejection LOGIC AND CONTROL INPUTS Input Low Level Input High Level ENLS, ENBUCK, ENLDO1, ENLDO2, ENLDO3, ENLDO45, ENUSB, SDA, SCL, 2.7V P VIN P 5.5V ENLS, ENBUCK, ENLDO1, ENLDO2, ENLDO3, ENLDO45, ENUSB, SDA, SCL, 2.7V P VIN P 5.5V 1.4 0.4 V V 2.7V P VIN P 5.5V 0.786 0.800 0.2 0.814 V mV/V TA rising 160 10 NC NC VIN_ rising VIN_ falling 2.70 2.85 2.35 3.05 2.55 V VCB = 0V or VIN, VENUSB = VIN, VENLS = VENBUCK = VENLDO1 = VENLDO2 = VENLDO3 = VENLDO45 = 0V No load on BUCK, LDO1, LDO2, LDO3, LDO4, and LDO5, VENUSB = 0V, VENLS = VIN BUCK on with 500FA load, all LDOs on with no load, VENUSB = 0V, VENLS = VIN CONDITIONS MIN 2.7 0.6 160 315 TYP MAX 5.5 5 200 UNIT V FA FA FA
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Notes 3, 4) PARAMETER Logic Input Current ENUSB Pullup Resistor to BATT ENLS, ENBUCK, ENLDO1, ENLDO2, ENLDO3, ENLDO45, Pulldown Resistor to AGND STEP-DOWN DC-DC CONVERTER (BUCK) Supply Current ILOAD = 0A, no switching 0.776 0.97 25 0.800 0.90 1.00 1.10 1.20 1.30 1.40 Programmable Output Voltage ILOAD = 100mA, programmable output voltage 0.8V to 2.4V in 100mV steps 1.50 1.60 1.70 1.80 1.90 2.00 2.10 2.20 2.231 2.328 Output-Voltage Line Regulation LX Leakage Current Current Limit On-Resistance Rectifier Off Current Threshold Minimum On- and Off-Times Shutdown Output Resistance VIN = 2.7V to 5.5V VLX = 0V or 5.5V p-MOSFET switch n-MOSFET rectifier p-MOSFET switch, ILX = -40mA n-MOSFET rectifier, ILX = 40mA ILXOFF tON, tOFF BUCK_ADEN = 1, VENBUCK = 0V TA = +25NC TA = +85NC 600 400 -1 0.1 990 700 0.65 0.4 30 70 300 1500 1300 2.300 2.400 0.3 +1 2.369 2.472 %/V FA mA I mA ns I V 1.03 0.824 FA CONDITIONS SDA, SCL, 0V < VIN < 5.5V TA = +25NC TA = +85NC 400 400 MIN -1 0.1 800 800 1600 1600 TYP MAX +1 UNIT FA kI kI
MAX8893A/MAX8893B/MAX8893C
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Notes 3, 4) PARAMETER LDO1 Input Voltage Range 2.7 1.552 1.600 1.70 1.80 1.90 2.00 2.10 2.20 2.30 Programmable Output Voltage ILOAD = 25mA, programmable output voltage 1.6V to 3.3V in 100mV steps 2.40 2.50 2.60 2.70 2.80 2.90 2.910 3.000 3.1 3.2 3.201 VIN = 5.5V with ILOAD = 1mA, and VIN = 3.2V with ILOAD = 300mA (MAX8893A) Output Voltage Accuracy VIN = 5.5V with ILOAD = 1mA, and VIN = 3.0V with ILOAD = 300mA (MAX8893B) VIN = 5.5V with ILOAD = 1mA, and VIN = 2.7V with ILOAD = 300mA (MAX8893C) Output Current Current Limit Dropout Voltage Load Regulation Power-Supply Rejection DVLDO1/DVIN2 Output Noise Voltage Output Capacitor for Stable Operation (Note 6) Ground Current Startup Time from Shutdown Shutdown Output Resistance VLDO1 = 0V ILOAD = 200mA, TA = +25NC 1mA < ILOAD < 300mA VENLDO1 = VBATT 10Hz to 10kHz, CLDO1 = 1FF, ILOAD = 30mA 100Hz to 100kHz, CLDO1 = 1FF, ILOAD = 30mA 0mA < ILOAD < 300mA 0mA < ILOAD < 150mA ILOAD = 500FA CLDO1 = 2.2FF, ILOAD = 300mA LDO1_ADEN = 1, VENLDO1 = 0V 1.4 0.7 550 200 25 75 45 2.2 1.0 21 40 300 2.716 2.522 1.746 3.300 2.800 2.600 1.800 3.399 2.884 2.678 1.854 300 mA mA mV mV dB FVRMS FF FA Fs I V 3.090 V 5.5 1.648 V CONDITIONS MIN TYP MAX UNIT
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Notes 3, 4) PARAMETER LDO2 Input Voltage Range 2.7 1.164 1.200 1.30 1.40 1.50 1.60 1.70 1.80 1.90 2.00 2.10 Programmable Output Voltage ILOAD = 25mA, programmable output voltage 1.2V to 3.3V in 100mV steps 2.134 2.200 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.201 Output Voltage Accuracy Output Current Current Limit Dropout Voltage Load Regulation Power-Supply Rejection DVLDO2/DVBATT Output Noise Voltage Output Capacitor for Stable Operation (Note 6) Ground Current Startup Time from Shutdown Shutdown Output Resistance VLDO2 = 0V ILOAD = 200mA, TA = +25NC 1mA < ILOAD < 300mA VENLDO2 = VBATT 10Hz to 10kHz, CLDO2 = 1FF, ILOAD = 30mA 100Hz to 100kHz, CLDO2 = 1FF, ILOAD = 30mA 0mA < ILOAD < 300mA 0mA < ILOAD < 150mA ILOAD = 500FA CLDO2 = 1FF, ILOAD = 300mA LDO2_ADEN = 1, VENLDO2 = 0V 1.4 0.7 550 200 25 60 80 2.2 1.0 21 40 300 VIN = 5.5V with ILOAD = 1mA, and VIN = 3.0V with ILOAD = 300mA 2.522 3.300 2.600 3.399 2.678 300 V mA mA mV mV dB FVRMS FF FA Fs I 2.266 V 5.5 1.236 V CONDITIONS MIN TYP MAX UNIT
MAX8893A/MAX8893B/MAX8893C
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Notes 3, 4) PARAMETER LDO3 Input Voltage Range 2.7 1.552 1.600 1.70 1.80 1.90 2.00 2.10 2.20 2.30 Programmable Output Voltage ILOAD = 25mA, programmable output voltage 1.6V to 3.3V in 100mV steps 2.40 2.50 2.60 2.70 2.80 2.90 2.910 3.000 3.10 3.20 3.201 Output Voltage Accuracy Output Current Current Limit Dropout Voltage Load Regulation Power-Supply Rejection DVLDO3/DVBATT Output Noise Voltage Output Capacitor for Stable Operation (Note 6) Ground Current Startup Time from Shutdown Shutdown Output Resistance VLDO3 = 0V ILOAD = 200mA, TA = +25NC 1mA < ILOAD < 300mA VENLDO3 = VBATT 10Hz to 10kHz, CLDO3 = 1FF, ILOAD = 30mA 100Hz to 100kHz, CLDO3 = 1FF, ILOAD = 30mA 0mA < ILOAD < 300mA 0mA < ILOAD < 150mA ILOAD = 500FA CLDO3 = 2.2FF, ILOAD = 300mA LDO3_ADEN = 1, VENLDO3 = 0V 1.4 0.7 550 200 25 60 80 2.2 1.0 21 40 300 VIN = 5.5V with ILOAD = 1mA, and VIN = 3.7V with ILOAD = 300mA 3.201 3.300 3.300 3.399 3.399 300 V mA mA mV mV dB FVRMS FF FA Fs I 3.090 V 5.5 1.648 V CONDITIONS MIN TYP MAX UNIT
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Notes 3, 4) LDO4 Input Voltage Range 2.7 0.776 0.800 0.90 1.00 1.10 1.20 1.30 1.358 1.400 1.50 1.60 1.70 1.80 1.90 Programmable Output Voltage ILOAD = 25mA, programmable output voltage 0.8V to 3.3V in 100mV steps 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.201 VIN = 5.5V with ILOAD=1mA, and VIN = 3.4V with ILOAD = 150mA (MAX8893A) VIN = 5.5V with ILOAD = 1mA, and VIN = 3.7V with ILOAD = 150mA (MAX8893B/MAX8893C) VLDO4 = 0V ILOAD = 100mA 1mA < ILOAD < 150mA, VENLDO4 = VBATT 10Hz to 10kHz, CLDO4 = 1FF, ILOAD = 30mA 100Hz to 100kHz, CLDO4 = 1FF, ILOAD = 30mA 0mA < ILOAD < 150mA (Note 6) 0.7 2.910 3.201 3.300 3.000 3.300 3.399 3.090 V 3.399 150 360 100 25 75 45 1.0 mA mA mV mV dB FVRMS FF V 1.442 5.5 0.824 V
MAX8893A/MAX8893B/MAX8893C
Output Voltage Accuracy
Output Current Current Limit Dropout Voltage Load Regulation Power-Supply Rejection DVLDO4/DVIN2 Output Noise Voltage Output Capacitor for Stable Operation
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Notes 3, 4) PARAMETER Ground Current Startup Time from Shutdown Shutdown Output Resistance LDO5 Input Voltage Range 2.7 0.776 0.800 0.90 1.00 1.10 1.20 1.30 1.358 1.400 1.50 1.60 1.70 1.80 1.90 Programmable Output Voltage ILOAD = 100mA, programmable output voltage 0.8V to 3.3V in 100mV steps 2.00 2.10 2.20 2.30 2.40 2.50 2.60 2.70 2.80 2.90 3.00 3.10 3.20 3.201 VIN = 5.5V with ILOAD = 1mA, and VIN = 3.4V with ILOAD = 150mA (MAX8893A) Output Voltage Accuracy VIN = 5.5V with ILOAD = 1mA, and VIN = 3.4V with ILOAD = 150mA (MAX8893B) VIN = 5.5V with ILOAD = 1mA, and VIN = 3.4V with ILOAD = 150mA (MAX8893C) Output Current Current Limit Dropout Voltage VLDO5 = 0V ILOAD = 100mA 460 100 0.970 2.716 2.910 3.300 1.000 2.800 3.000 3.399 1.030 2.884 3.090 200 mA mA mV V V 1.442 5.5 0.824 V ILOAD = 500FA CLDO4 = 1.0FF, ILOAD = 150mA LDO4_ADEN = 1, VENLDO4 = 0V CONDITIONS MIN TYP 21 40 300 MAX UNIT FA Fs I
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Notes 3, 4) PARAMETER Load Regulation Power-Supply Rejection DVLDO5/DVIN2 Output Noise Voltage Output Capacitor for Stable Operation (Note 6) Ground Current Startup Time from Shutdown Shutdown Output Resistance USB HIGH-SPEED SWITCH Operating Power-Supply Range Supply Current Fault Protection Trip Threshold (VFP) On-Resistance (RON) On-Resistance Match Between Channels (DRON) On-Resistance Flatness (RFLAT) Off-Leakage Current (ICOM_(OFF)) VENUSB = 0V, VCB = 0V or VBATT COM_ only, TA = +25NC VCOM_ = 0V to VBATT VCOM_ = 3.6V, VBATT = 3.0V VBATT = 3.0V, VCOM_ = 2V (Note 7) VBATT = 3.0V, VCOM_ = 0V to VIN (Note 8) VBATT = 4.5V, VCOM_ = 0V or 4.5V, VNO_, VNC_ = 4.5V or 0V VBATT = 5.5V, VCOM_ = 0V or 5.5V, VNO_, VNC_ with 50FA sink current to AGND VBATT = 5.5V, VCOM_ = 0V or 5.5V, VNO_, and VNC_ are unconnected -250 -250 VBATT = 3.0V VBATT = 5.5V VIN + 0.6 2.7 0.6 3 VIN + 0.8 5 5.5 0.1 0.1 +250 180 +250 1 VIN + 1.0 10 5.5 V FA V I I I nA FA nA CONDITIONS 1mA < ILOAD < 150mA VENLDO5 = VBATT 10Hz to 10kHz, CLDO5 = 1FF, ILOAD = 30mA 100Hz to 100kHz, CLDO5 = 1FF, ILOAD = 30mA 0mA < ILOAD < 200mA 0mA < ILOAD < 150mA ILOAD = 500FA CLDO5 = 2.2FF, ILOAD = 200mA LDO5_ADEN = 1, VENLDO5 = 0V 1.4 0.7 MIN TYP 25 75 45 2.2 1.0 21 40 300 MAX UNIT mV dB FVRMS FF FA Fs I
MAX8893A/MAX8893B/MAX8893C
On-Leakage Current (ICOM_(ON))
USB HIGH-SPEED SWITCH AC PERFORMANCE On-Channel -3dB Bandwidth (BW) Off-Isolation (VISO) RL = RS = 50I, signal = 0dBm VNO_, VNC_ = 0dBm, RL = RS = 50I, Figure 1 VNO_, VNC_ = 0dBm, RL = RS = 50I, Figure 1 (Note 9) f = 10MHz f = 250MHz f = 500MHz f = 10MHz f = 250MHz f = 500MHz 1.4 0.4 -250 +250 950 -48 -20 -17 -73 -54 -33 V V nA dB dB MHz
Crosstalk (VCT)
USB HIGH-SPEED SWITCH LOGIC INPUT (CB) Input Logic-High (VIH) Input Logic-Low (VIL) Input Leakage Current (IIN)
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Notes 3, 4) PARAMETER USB HIGH-SPEED SWITCH DYNAMIC Turn-On Time (tON) Turn-Off Time (tOFF) Propagation Delay (tPLH, tPHL) Fault Protection Response Time (tFP) Fault Protection Recovery Time (tFPR) Output Skew Between Switches (tSK) NO_ or NC_ Off-Capacitance (CNO(OFF) or CNC(OFF)) COM Off-Capacitance (CCOM(OFF)) (Note 6) COM On-Capacitance (CCOM(ON)) (Note 6) Total Harmonic Distortion Plus Noise ENUSB, CB, NC1, NC2, NO1, NO2 COM1, COM2 VNO_ or VNC_ = 1.5V, RL = 300I, CL = 35pF, V/ENUSB = VBATT to 0V, Figure 2 VNO_ or VNC_ = 1.5V, RL = 300I, CL = 35pF, V/ENUSB = 0V to VBATT, Figure 2 RL = RS = 50I, Figure 3 VCOM_ = 0V to 5V step, RL = RS = 50I, VBATT = 3.3V, Figure 4 VCOM_ = 5V to 0V step, RL = RS = 50I, VBATT = 3.3V, Figure 4 Skew between switch 1 and 2, RL = RS = 50I, Figure 3 (Note 6) f = 1MHz, Figure 5 (Note 6) f = 1MHz, Figure 5 f = 240 MHz, Figure 5 f = 1MHz, Figure 5 f = 240 MHz, Figure 5 VCOM_ = 1VP-P, VBIAS = 1V, RL = RS = 50I, f = 20Hz to 20kHz 40 2 5.5 4.8 6.5 5.5 0.03 0.5 1 1 100 5.0 100 5 5 Fs Fs ps Fs Fs ps pF pF pF % CONDITIONS MIN TYP MAX UNIT
USB HIGH-SPEED SWITCH--ESD PROTECTION Human Body Model Human Body Model IEC 61000-4-2 Air-Gap Discharge IEC 61000-4-2 Contact Discharge I2C SERIAL INTERFACE (Figure 8) Clock Frequency Bus-Free Time Between START and STOP (tBUF) Hold Time Repeated START Condition (tHD_STA) SCL Low Period (tLOW) SCL High Period (tHIGH) Setup Time Repeated START Condition (tSU_STA) SDA Hold Time (tHD_DAT) SDA Setup time (tSU_DAT) Setup Time for STOP Condition (tSU_STO) 1.3 0.6 1.3 0.6 0.6 0 100 0.6 400 kHz Fs Fs Fs Fs Fs Fs ns Fs 2 15 15 8 kV kV
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
ELECTRICAL CHARACTERISTICS (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at TA = +25NC.) (Notes 3, 4) PARAMETER Maximum Pulse Width of Spikes Suppressed LOAD SWITCH (LS) Input Supply Operating Range (VBUCK) On-Resistance (RDS(ON)) After VBUCK starts up VBUCK = 1.0V, ILS = 300mA, TA = +25NC VLS = 2.4V, RL = 400I, VENLS = 1.8V, Register LSTOD = 0 (Note 6) Turn-On Delay Time (tON_DLY) VLS = 2.4V, RL = 400I, VENLS = 1.8V, Register LSTOD = 1 VLS = 2.4V, RL = 400I, VENLS = 1.8V, Register LSRT = 0 VLS = 2.4V, RL = 400I, VENLS = 1.8V, Register LSRT = 1 VLS = 2.4V, RL = 400I, VENLS = 1.8V, Register LSRT = 2 VLS = 2.4V, RL = 400I, VENLS = 1.8V, Register LSRT = 3 VLS = 2.4V, RL = 400I, VENLS = 1.8V VLS = 2.4V, RL = 400I, VENLS = 1.8V CL = 0.1FF CL = 1FF CL = 3FF CL = 0.1FF CL = 1FF CL = 3FF CL = 0.1FF CL = 1FF (Note 6) CL = 3FF (Note 6) CL = 0.1FF CL = 1FF CL = 3FF CL = 0.1FF CL = 1FF CL = 3FF CL = 0.1FF CL = 1FF CL = 3FF CL = 0.1FF CL = 1FF CL = 3FF CL = 0.1FF CL = 1FF CL = 3FF 0.8 50 0.85 0.85 0.85 30 34 37 10 10 10 25 27 30 100 100 100 300 300 300 11 11 11 15 150 447 100 200 I Fs Fs Fs Fs 2.4 100 V mI CONDITIONS MIN TYP 50 MAX UNIT ns
MAX8893A/MAX8893B/MAX8893C
LS Rise Time (tR)
Turn-Off Delay Time (tOFF_DLY)
LS Fall Time (tF) Shutdown Output Resistance
VLS = 2.4V, VENLS = 0V, LS_ADEN = 1
Note 3: VIN1, VIN2, and VBATT are connected together and single input is referred to as VIN. Note 4: All units are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by design. Note 5: When the input voltage is greater than 2.85V (typ), the UVLO comparator trips, and the threshold is reduced to 2.35V (typ). This allows the system to start normally even if the input voltage decays to 2.35V. Note 6: Not production tested; guaranteed by design. Note 7: DRON(MAX) = |RON(CH1) - RON(CH2)|. Note 8: Flatness is defined as the difference between the maximum and minimum value of on-resistance, as measured over specified analog signal ranges. Note 9: Between any two switches.
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
Typical Operating Characteristics
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
NO-LOAD SUPPLY CURRENT vs. SUPPLY VOLTAGE
STEP-DOWN AND ALL LDOs ENUSB = GND, ENLS = BATT
MAX8893A toc01
NO-LOAD SUPPLY CURRENT vs. TEMPERATURE
190 180 SUPPLY CURRENT (A) 170 160 150 140 130 120 110 100 VBATT = 3.7V VBATT = 4.2V VBATT = 3.0V
MAX8893A toc02
250 200 SUPPLY CURRENT (A) 150 100 50 STEP-DOWN ONLY 0 2.5 3.0 3.5 4.0 4.5 5.0 STEP-DOWN AND ALL LDOs ENUSB = BATT, ENLS = GND
200
5.5
-40
-15
10
35
60
85
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
USB SWITCH ON-RESISTANCE vs. COM VOLTAGE
MAX8893A toc03
USB SWITCH ON-RESISTANCE vs. COM VOLTAGE
TA = +85C TA = +60C TA = +35C TA = +10C TA = -15C TA = -40C VBATT = 3.7V 2.5 6 0 1 2 3 4 5
MAX8893A toc04 MAX8893A toc06
5.5 TA = +25C 5.0 ON-RESISTANCE (I) 4.5 4.0 3.5 3.0 2.5 0 1 2 3 4 5 COM VOLTAGE (V) VBATT = 3.0V
5.5 5.0 ON-RESISTANCE (I) 4.5 4.0 3.5 3.0
VBATT = 3.7V VBATT = 4.2V FAULT PROTECTION
COM VOLTAGE (V)
COM LEAKAGE CURRENT vs. TEMPERATURE
MAX8893A toc05
LOGIC THRESHOLD VOLTAGE vs. SUPPLY VOLTAGE
1.4 1.2 THRESHOLD VOLTAGE (V) 1.0 0.8 0.6 0.4 0.2 0 FALLING RISING
45 43 41 39 37 35 -40 -15 10 35 60
COM LEAKAGE CURRENT (nA)
85
2.5
3.0
3.5
4.0
4.5
5.0
5.5
TEMPERATURE (C)
SUPPLY VOLTAGE (V)
12
_____________________________________________________________________________________
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
LOAD SWITCH ON-RESISTANCE vs. TEMPERATURE
MAX8893A toc07
MAX8893A/MAX8893B/MAX8893C
LOAD SWITCH ON-RESISTANCE vs. BATTERY VOLTAGE
MAX8893A toc08
90 80 ON-RESISTANCE (mI) 70 60 50 VBUCK = 1.0V, ILS = 500mA 40 -40 -15 10 35 60
90 80 ON-RESISTANCE (mI) 70 60 50 VBUCK = 1.0V 40 2.5 3.0 3.5 4.0 4.5 5.0
85
5.5
TEMPERATURE (C)
BATTERY VOLTAGE (V)
LOAD SWITCH TURN-ON/OFF WAVEFORM
MAX8893A toc09
LOAD SWITCH TURN-ON/OFF WAVEFORM
MAX8893A toc10
VENLS
2V/div
VENLS
2V/div
VLS
500mV/div
VLS
500mV/div
ILS 10I LOAD, CLS = 1.0F 20s/div
200mA/div
ILS 20s/div
2I LOAD CLS = 1.0F
500mA/div
LOAD SWITCH VOLTAGE DROP vs. LOAD CURRENT
MAX8893A toc11
STEP-DOWN EFFICIENCY vs. LOAD CURRENT
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 VBUCK = 1.0V 0.1 1.0 10 100 1000 LOAD CURRENT (mA) VBATT = 3.7V VBATT = 4.2V VBATT = 3.0V
MAX8893A toc12
40 VBUCK = 1.0V 30 VBUCK - VLS (mV)
100
20
10
0 0 100 200 300 400 500 LOAD CURRENT (mA)
______________________________________________________________________________________
13
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
STEP-DOWN SWITCHING FREQUENCY vs. LOAD CURRENT
3600 SWITCHING FREQUENCY (kHz) 3200 2800 2400 2000 1600 1200 800 400 0 0 100 200 300 400 500 LOAD CURRENT (mA) VBATT = 3.7V VBUCK = 1.0V
MAX8893A toc13
STEP-DOWN OUTPUT VOLTAGE vs. LOAD CURRENT
MAX8893A toc14
4000
1.02 1.01 OUTPUT VOLTAGE (V) VBATT = 3.7V 1.00 0.99 0.98 0.97 0 100 200 300 400 VBATT = 3.0V VBUCK = 1.0V VBATT = 4.2V
500
LOAD CURRENT (mA)
STEP-DOWN LIGHT-LOAD SWITCHING WAVEFORMS
MAX8893A toc15
STEP-DOWN MEDIUM-LOAD SWITCHING WAVEFORMS
MAX8893A toc16
VBUCK VBUCK 50mV/div (AC-COUPLED)
20mV/div (AC-COUPLED)
VLX
2V/div
VLX
2V/div
IL
1mA LOAD, VBUCK = 1.0V 10s/div
100mA/div
IL
40mA LOAD, VBUCK = 1.0V 400ns/div
100mA/div
STEP-DOWN HEAVY-LOAD SWITCHING WAVEFORMS
MAX8893A toc17
STEP-DOWN STARTUP AND SHUTDOWN WAVEFORM
MAX8893A toc18
VBUCK
20mV/div (AC-COUPLED)
VENBUCK
2V/div
VLX
2V/div
VBUCK 500mA LOAD, VBUCK = 1.0V
500mV/div
IL
300mA LOAD, VBUCK = 1.0V 400ns/div
200mA/div
IIN
100mA/div
100s/div
14
_____________________________________________________________________________________
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
MAX8893A/MAX8893B/MAX8893C
STEP-DOWN LINE TRANSIENT WAVEFORM
MAX8893A toc19
STEP-DOWN LOAD TRANSIENT WAVEFORM
MAX8893A toc20
4V VBATT 3.5V
500mV/div
VBUCK
50mV/div
VBUCK
20mA/div (AC-COUPLED) IOUT 10I LOAD 10s/div 5mA
300mA 5mA
200mA/div
20s/div
LDO1 DROPOUT VOLTAGE vs. LOAD CURRENT
MAX8893A toc21
LDO1 OUTPUT-VOLTAGE ERROR vs. LOAD CURRENT
MAX8893A toc22
200
0 OUTPUT-VOLTAGE ERROR (mV) -10 -20 -30 -40 -50
DROPOUT VOLTAGE (mV)
150
100
50
0 0 50 100 150 200 250 300 LOAD CURRENT (mA)
0
50
100
150
200
250
300
LOAD CURRENT (mA)
LDO1 OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX8893A toc23
LDO1 LINE TRANSIENT WAVEFORM
MAX8893A toc24
2.80 2.75 OUTPUT VOLTAGE (V) 2.70 2.65 2.60 2.55 300mA LOAD 2.50 2.7 3.1 3.5 3.9 4.3 4.7 5.1
4V VBATT 3.5V
500mV/div
VLDO1
10mV/div (AC-COUPLED)
10I LOAD 5.5 10s/div
INPUT VOLTAGE (V)
______________________________________________________________________________________
15
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
LDO1 LOAD TRANSIENT WAVEFORM
MAX8893A toc25
LDO1 STARTUP AND SHUTDOWN WAVEFORM
MAX8893A toc26
300mA 5mA 5mA
VENLOD1
2V/div
IOUT
200mA/div VLDO1 200mV/div (AC-COUPLED) IIN 1V/div
VLDO1
300mA LOAD, VLDO1 = 2.8V 500mA/div
20s/div
100s/div
LDO2 DROPOUT VOLTAGE vs. LOAD CURRENT
MAX8893A toc27
LDO2 OUTPUT-VOLTAGE ERROR vs. LOAD CURRENT
MAX8893A toc28
200
0 OUTPUT-VOLTAGE ERROR (mV) -10 -20 -30 -40 -50
DROPOUT VOLTAGE (mV)
150
100
50
0 0 50 100 150 200 250 300 LOAD CURRENT (mA)
0
50
100
150
200
250
300
LOAD CURRENT (mA)
LDO2 OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX8893A toc29
LDO2 LINE TRANSIENT WAVEFORM
MAX8893A toc30
2.65
4V VBATT 3.5V
500mV/div
OUTPUT VOLTAGE (V)
2.60
2.55 VLDO2 2.50 300mA LOAD 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 10I LOAD 10s/div 10mV/div (AC-COUPLED)
2.45
INPUT VOLTAGE (V)
16
_____________________________________________________________________________________
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
MAX8893A/MAX8893B/MAX8893C
LDO2 LOAD TRANSIENT WAVEFORM
MAX8893A toc31
LDO2 STARTUP AND SHUTDOWN WAVEFORM
MAX8893A toc32
300mA 5mA 5mA
VENLDO2
2V/div
IOUT
200mA/div VLDO2 200mV/div (AC-COUPLED) IIN 1V/div
VLDO1
300mA LOAD, VLDO2 = 2.6V 500mA/div
20s/div
100s/div
LDO3 DROPOUT VOLTAGE vs. LOAD CURRENT
MAX8893A toc33
LDO3 OUTPUT-VOLTAGE ERROR vs. LOAD CURRENT
MAX8893A toc34
200
0 OUTPUT-VOLTAGE ERROR (mV) -10 -20 -30 -40 -50
DROPOUT VOLTAGE (mV)
150
100
50
0 0 50 100 150 200 250 300 LOAD CURRENT (mA)
0
50
100
150
200
250
300
LOAD CURRENT (mA)
LDO3 OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX8893A toc35
LDO3 LINE TRANSIENT WAVEFORM
MAX8893A toc36
3.3 3.2 OUTPUT VOLTAGE (V) 3.1 3.0 2.9 2.8 2.7 2.6 2.5 2.7 3.1
300mA LOAD
4V VBATT 3.5V
500mV/div
VLDO3
10mV/div (AC-COUPLED)
10I LOAD
3.5 3.9 4.3 4.7 INPUT VOLTAGE (V)
5.1
5.5
10s/div
______________________________________________________________________________________
17
FPMIC for Multimedia Application Processor in 2.5mm x 3.0mm WLP MAX8893A/MAX8893B/MAX8893C
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
LDO3 STARTUP AND SHUTDOWN WAVEFORM
MAX8893A toc38
LDO3 LOAD TRANSIENT WAVEFORM
MAX8893A toc37
300mA
5mA
VENLDO3 5mA
2V/div
IOUT
200mA/div VLDO3 2V/div
VLDO3 200mV/div (AC-COUPLED) IIN 300mA LOAD, VLDO3 = 3.3V 500mA/div
20s/div
100s/div
LDO4 DROPOUT VOLTAGE vs. LOAD CURRENT
MAX8893A toc39
OUTPUT-VOLTAGE ERROR (mV)
DROPOUT VOLTAGE (mV)
80 60 40 20 0 0 30 60 90 120
-10 -20 -30 -40 -50 0 30 60 90 120
150
150
LOAD CURRENT (mA)
LOAD CURRENT (mA)
18
_____________________________________________________________________________________
MAX8893A toc40
100
LDO4 OUTPUT-VOLTAGE ERROR vs. LOAD CURRENT
0
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
LDO4 OUTPUT VOLTAGE INPUT VOLTAGE
MAX8893A toc41
MAX8893A/MAX8893B/MAX8893C
LDO4 LINE TRANSIENT WAVEFORM
MAX8893A toc42
3.0 2.9 OUTPUT VOLTAGE (V) 2.8 2.7 2.6 2.5 2.7 3.1 3.5 3.9 4.3 150mA LOAD 4.7 5.1
4V VBATT 3.5V
500mV/div
VLDO4
10mV/div (AC-COUPLED)
20I LOAD 5.5 10s/div
INPUT VOLTAGE (V)
LDO4 LOAD TRANSIENT WAVEFORM
MAX8893A toc43
LDO5 DROPOUT VOLTAGE vs. LOAD CURRENT
MAX8893A toc44
150 120 90 60 30 0 0 40 80 120 160
IOUT
5mA
5mA
200mA/div
VLDO4
200mV/div (AC-COUPLED)
20s/div
DROPOUT VOLTAGE (mV)
150mA
200
LOAD CURRENT (mA)
______________________________________________________________________________________
19
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
LDO4 OUTPUT-VOLTAGE ERROR vs. LOAD CURRENT
MAX8893A toc45
LDO5 OUTPUT VOLTAGE vs. INPUT VOLTAGE
MAX8893A toc46
0 OUTPUT-VOLTAGE ERROR (mV) -10 -20 -30 -40 -50 0 40 80 120 160
1.02 1.01 OUTPUT VOLTAGE (V) 1.00 0.99 0.98 200mA LOAD 0.97
200
2.7
3.1
3.5
3.9
4.3
4.7
5.1
5.5
LOAD CURRENT (mA)
INPUT VOLTAGE (V)
LDO5 LINE TRANSIENT WAVEFORM
MAX8893A toc47
LDO5 LOAD TRANSIENT WAVEFORM
MAX8893A toc48
4V VBATT 3.5V
500mV/div 200mA IOUT 5mA 5mA 200mA/div
VLDO5
10mV/div (AC-COUPLED)
VLDO5
200mV/div (AC-COUPLED)
5I LOAD 10s/div 20s/div
LDO4 AND LDO5 STARTUP AND SHUTDOWN WAVEFORM
MAX8893A toc49
POWER-UP SEQUENCING (MAX8893A)
MAX8893A toc50
VENLDO45 VLDO4
2V/div 2V/div
VEN_ VBUCK VLDO1
1.0V 2.8V 2.6V 3.3V 3.0V 1.0V 5I LOAD
2V/div 2V/div 4V/div 4V/div 5V/div 5V/div 2V/div
VLDO5 VLDO4 = 3.0V, 150mA LOAD VLDO5 = 1.0V, 200mA LOAD
VLDO2 1V/div VLDO3 VLDO4 500mA/div VLDO5
IIN
100s/div
100s/div
20
_____________________________________________________________________________________
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
Typical Operating Characteristics (continued)
(Typical Operating Circuit, VIN = 3.7V, CBATT = CIN1 = CIN2 = 2.2FF, CREFBP = 0.1FF, TA = +25NC, unless otherwise noted.)
MAX8893A/MAX8893B/MAX8893C
POWER-UP SEQUENCING (MAX8893B)
MAX8893A toc51
POWER-UP SEQUENCING (MAX8893C)
MAX8893A toc52
VEN_ VBUCK VLDO1 VLDO2 VLDO3 VLDO4 VLDO5
1.0V 2.6V 2.6V 3.3V 3.3V 2.8V
2V/div 2V/div 4V/div 4V/div 5V/div 5V/div 5V/div
VEN_ VBUCK VLDO1 VLDO2 VLDO3 VLDO4 VLDO5
1.0V 1.8V 2.6V 3.3V 3.3V 3.0V
2V/div 2V/div 4V/div 4V/div 5V/div 5V/div 5V/div
100s/div
100s/div
TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
RL = 600I
MAX8893A toc53
FREQUENCY RESPONSE
-10 -20 MAGNITUDE (dB) -30 -40 -50 -60 -70 -80 -90
ON-LOSS OFF-ISOLATION
0.1 THD+N (%)
0.01
CROSSTALK
0.001 10 100 1000 FREQUENCY (Hz) 10,000 100,000
-100 1 10 100 1000 FREQUENCY (MHz)
EYE DIAGRAM
MAX8893A toc55
DIFFERENTIAL SIGNAL (V)
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 TIME (x 10-9)s
______________________________________________________________________________________
MAX8893A toc54
1
0
21
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
Test Circuits/Timing Diagrams
0V OR VCC
CB
COM1
VIN
50I
NETWORK ANALYZER
OFF-ISOLATION = 20log 50I CROSSTALK = 20log
VOUT VIN VOUT VIN
NC1 50I
MAX8893A MAX8893B MAX8893C
NO1*
VOUT
MEAS 50I
REF 50I
SWITCH IS ENABLED. MEASUREMENTS ARE STANDARDIZED AGAINST SHORTS AT IC TERMINALS. OFF-ISOLATION IS MEASURED BETWEEN COM_ AND "OFF" NO_ OR NC_ TERMINAL ON EACH SWITCH. CROSSTALK IS MEASURED FROM ONE CHANNEL TO THE OTHER CHANNEL. SIGNAL DIRECTION THROUGH SWITCH IS REVERSED; WORST VALUES ARE RECORDED.
*FOR CROSSTALK THIS PIN IS NO2. NC2 AND COM2 ARE OPEN.
Figure 1. USB High-Speed Switch Off-Isolation and Crosstalk
MAX8893A MAX8893B MAX8893C VIN_ NO_ OR NC_ EN (EN) LOGIC INPUT COM RL CL VOUT
LOGIC INPUT
VIH VIL 50%
t R < 5ns t F < 5ns
t OFF VOUT SWITCH OUTPUT 0V t ON IN DEPENDS ON SWITCH CONFIGURATION; INPUT POLARITY DETERMINED BY SENSE OF SWITCH. 0.9 x V0UT
0.1 x VOUT
CL INCLUDES FIXTURE AND STRAY CAPACITANCE. RL VOUT = VIN_ RL + RON
(
)
Figure 2. USB High-Speed Switch Switching Time
22
_____________________________________________________________________________________
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
Test Circuits/Timing Diagrams (continued)
MAX8893A/MAX8893B/MAX8893C
VIN+
RS
NC1 OR NO1
MAX8893A MAX8893B MAX8893C COM1 RL VOUT+ tPLH = tPLHX OR tPLHY tPHL = tPHLX OR tPHLY tSK(O) = |tPLHX - tPLHY| OR |tPHLX - tPHLY| tSK(P) = |tPLHX - tPHLX| OR |tPLHY - tPHLY| VOUTRL CB VIL TO VIH tINRISE tINFALL
VIN-
RS
NC2 OR NO2
COM2
VCC VIN+ 0V VCC VIN0V 50% 50% 50% 50% 10%
90%
90% 10%
tOUTRISE tPLHX VCC VOUT+ 0V VCC VOUT0V tPHLY tPLHY 50% 50% 50% 50% 10% tPHLX 90% 90%
tOUTFALL
10%
Figure 3. USB High-Speed Switch Output Signal Skew, Rise/Fall Time, Propagation Delay
______________________________________________________________________________________
23
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
Test Circuits/Timing Diagrams (continued)
VCC = 3.3V
5V 3V
VCOM tFP tFPR
COM 0V CAPACITANCE METER VFP
MAX8893A MAX8893B MAX8893C CB VIL OR VIH
NC_ OR NO_
VNO_ VNC_
3V 0V
Figure 4. USB High-Speed Switch Fault-Protection Response/ Recovery Time
Figure 5. USB High-Speed Switch Channel Off-/On-Capacitance
Pin Configuration
TOP VIEW (BUMPS ON BOTTIOM)
1 2 3 4 5 6
MAX8893A/MAX8893B/MAX8893C
A LDO1 LDO2 LDO3 BATT IN1 LX
B
REFBP
CB
ENUSB
ENLDO1
ENBUCK
PGND
C
IN2
NC1
NC2
ENLDO2
ENLS
BUCK
D
LDO5
NO1
NO2
ENLDO3
ENLDO45
SCL
E
LDO4
COM1
COM2
AGND
LS
SDA
WLP (3.0mm x 2.5mm)
24
_____________________________________________________________________________________
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
Pin Description
PIN A1 NAME LDO1 FUNCTION 300mA LDO1 Output. Bypass LDO1 to AGND with a 2.2FF ceramic capacitor. The output voltage is programmable from 1.6V to 3.3V in 100mV steps. The output impedance of LDO1 is 300I when disabled with the LDO1_ADEN bit set to 1. 300mA LDO2 Output. Bypass LDO2 to AGND with a 2.2FF ceramic capacitor. The output voltage is programmable from 1.2V to 3.3V in 100mV steps. The output impedance of LDO2 is 300I when disabled with the LDO2_ADEN bit set to 1. 300mA LDO3 Output. Bypass LDO3 to AGND with a 2.2FF ceramic capacitor. The output voltage is programmable from 1.6V to 3.3V in 100mV steps. The output impedance of LDO3 is 300I when disabled with the LDO3_ADEN bit set to 1. Supply Voltage to the Control Section, LDO2, LDO3, and USB Switch. Connect a 2.2FF ceramic capacitor from BATT to AGND. Supply Voltage to the Step-Down Converter. Connect a 2.2FF input ceramic capacitor from IN1 to PGND. Inductor Connection for Step-Down Converter. LX is internally connected to the drain of the internal p-channel MOSFET and the drain of the internal n-channel synchronous rectifier. The output impedance of LX is 300I when the step-down converter is disabled with the BUCK_ADEN bit set to 1. Reference Noise Bypass. Bypass REFBP to AGND with a 0.1FF ceramic capacitor to reduce noise on the LDO outputs. REFBP is high impedance in shutdown. Digital Control Input for USB High-Speed Switch. Drive CB low to connect COM1 to NC1 and COM2 to NC2. Drive CB high to connect COM1 to NO1 and COM2 to NO2. Active-Low Enable Input for USB High-Speed Switch. Drive ENUSB high to put the switch in high impedance. Drive ENUSB low for normal operation. Enable Input for LDO1. Drive ENLDO1 high to turn on the LDO1. Drive ENLDO1 low to turn off the LDO1. LDO1 can also be enabled/disabled through the I2C interface. ENLDO1 and I2C control bit are logically ORed. ENLDO1 has an internal 800kI pulldown resistor. Enable Input for the Step-Down Converter. Drive ENBUCK high to turn on the step-down converter. Drive ENBUCK low to turn off the step-down converter. The step-down converter can also be enabled/ disabled through the I2C interface. ENBUCK and I2C control bit are logically ORed. ENBUCK has an internal 800kI pulldown resistor. Power Ground for Step-Down Converter Supply Voltage to LDO1, LDO4, and LDO5. Connect a 2.2FF input ceramic capacitor from IN2 to AGND.
MAX8893A/MAX8893B/MAX8893C
A2
LDO2
A3
LDO3
A4 A5
BATT IN1
A6
LX
B1 B2 B3
REFBP CB ENUSB
B4
ENLDO1
B5
ENBUCK
B6 C1
PGND IN2
______________________________________________________________________________________
25
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
Pin Description (continued)
PIN C2 C3 C4 NAME NC1 NC2 ENLDO2 FUNCTION Normally Closed Terminal for USB Switch 1. NC1 is high impedance in shutdown. Normally Closed Terminal for USB Switch 2. NC2 is high impedance in shutdown. Enable Input for LDO2. Drive ENLDO2 high to turn on the LDO2. Drive ENLDO2 low to turn off the LDO2. LDO2 can also be enabled/disabled through the I2C interface. ENLDO2 and I2C control bit are logically ORed. ENLDO2 has an internal 800kI pulldown resistor. Enable Input for Load Switch. Drive ENLS high to turn on the load switch. Drive ENLS low to turn off the load switch. The load switch can also be enabled/disabled through the I2C interface. ENLS and I2C control bit are logically ORed. ENLS has an internal 800kI pulldown resistor. Voltage Feedback for Step-Down Converter 200mA LDO5 Output. Bypass LDO5 to AGND with a 2.2FF ceramic capacitor. The output voltage of LDO5 is programmable from 0.8V to 3.3V in 100mV steps. The output impedance of LDO5 is 300I when disabled with the LDO5_ADEN bit set to 1. Normally Open Terminal for USB Switch 1. NO1 is high impedance in shutdown. Normally Open Terminal for USB Switch 2. NO2 is high impedance in shutdown. Enable Input for LDO3. Drive ENLDO3 high to turn on the LDO3. Drive ENLDO3 low to turn off the LDO3. LDO3 can also be enabled/disabled through the I2C interface. ENLDO3 and I2C control bit are logically ORed. ENLDO3 has an internal 800kI pulldown resistor. Enable Input for LDO4 and LDO5. Drive ENLDO45 high to turn on the LDO4 and LDO5. Drive ENLDO45 low to turn off the LDO4 and LDO5. LDO4 and LDO5 can also be enabled/disabled individually through the I2C interface. ENLDO45 and I2C control bits (ELDO4 and ELDO5) are logically ORed. ENLDO45 has an internal 800kI pulldown resistor. I2C-Compatible Serial Interface Clock High-Impedance Input 150mA LDO4 Output. Bypass LDO4 to GND with a 1FF ceramic capacitor. The output voltage of LDO4 is programmable from 0.8V to 3.3V in 100mV steps. The output impedance of LDO4 is 300I when disabled with the LDO4_ADEN bit set to 1. Common Terminal for USB High Switch 1 Common Terminal for USB High Switch 2 Analog Ground. Ground for all the LDOs, control section, and USB switches. Load Switch Output. LS is connected to the drain of an internal p-channel MOSFET. VLS = VBUCK RDS(ON) (p-channel MOSFET) x load current. I2C-Compatible Serial Interface Data High-Impedance Input
C5 C6 D1 D2 D3 D4
ENLS BUCK LDO5 NO1 NO2 ENLDO3
D5
ENLDO45
D6 E1 E2 E3 E4 E5 E6
SCL LDO4 COM1 COM2 AGND LS SDA
26
_____________________________________________________________________________________
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
CIN2 2.2F CBATT 2.2F CIN1 2.2F Li+ BATTERY
IN2 AGND
BATT
IN1
LS CLS 1F EN ENLS
MAX8893A MAX8893B MAX8893C
LOAD SWITCH CONTROL
IN
VBUCK LX STEP-DOWN CONVERTER PGND EN
BUCK LX 2.2H VBUCK, 0.8V TO 2.4V 100mV STEP, 500mA CBUCK 2.2F PGND ENBUCK
ENBUCK VLDO1, 1.6V TO 3.3V 100mV STEP, 300mA CLDO1 2.2F
IN LDO1 ANALOG LDO
OUT
LDO1
SDA SCL
SDA SCL I2C AND LOGIC IN
EN OUT
ENLDO1 LDO2
ENLDO1 VLDO2, 1.2V TO 3.3V 100mV STEP, 300mA CLDO2 2.2F
LDO2
REFBP CREFBP 0.1F IN
EN OUT
ENLDO2 LDO3
ENLDO2 VLDO3, 1.6V TO 3.3V 100mV STEP, 300mA CLDO3 2.2F
LDO3 ENLDO3 LDO4
EN IN LDO4 ANALOG LDO EN IN LDO5 ANALOG LDO OUT OUT
ENLDO3 VLDO4, 0.8V TO 3.3V 100mV STEP, 150mA CLDO4 1.0F
ENLDO45 LDO5
ENLDO45 VLDO5, 0.8V TO 3.3V 100mV STEP, 200mA CLDO5 2.2F
EN ENUSB USBSEL ENUSB CB COM1 COM2 EN IN USB HIGH S/W NC1 NC2 NO1 NO2
Figure 6. Block Diagram and Application Circuit ______________________________________________________________________________________ 27
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
Detailed Description
The MAX8893A/MAX8893B/MAX8893C highly integrated power-management ICs integrate a high-efficiency 500mA step-down DC-DC converter, five low-dropout linear regulators, a load switch with ultra-low on-resistance, a USB high-speed switch, and a 400kHz I2C serial interface. The step-down converter delivers over 500mA at I2C programmable output levels from 0.8V to 2.4V. It uses a proprietary hysteretic-PWM control scheme that switches up to 4MHz, allowing a trade-off between efficiency and tiny external components. The step-down converter also features dynamic voltage scaling (DVS) control. Its output voltage ramps up with the I2C-controlled ramp rate from 1mV/Fs to 12mV/Fs. Five low-dropout linear regulators feature low 45FVRMS output noise (LDO1, LDO4, and LDO5) and very low ground currents (LDO2 and LDO3). The USB high-speed switch is a high ESD-protected DPDT analog switch. It is ideal for USB 2.0 Hi-Speed (480Mbps) switching applications and also meets USB low- and full-speed requirements. The load switch features ultra-low on-resistance and operates from 0.8V to 2.4V input range. Its rise time is I2C programmable to control the inrush current. The internal I2C interface provides flexible control on regulator ON/OFF control, output voltage setting, step-down dynamic voltage scaling and ramp rate, and load switch timing. remains off until the minimum off-time (tOFF) expires and the output voltage again falls below the regulation threshold. During the off period, the low-side synchronous rectifier turns on and remains on until either the high-side switch turns on again or the inductor current reduces to the rectifier-off current threshold (ILXOFF = 30mA (typ)). The internal synchronous rectifier eliminates the need for an external Schottky diode. The step-down converter has the internal soft-start circuitry with a fixed ramp to eliminate input current spikes when it is enabled. Voltage Positioning Load Regulation The step-down converter uses a unique feedback network. By taking feedback from the LX node, the usual phase lag due to the output capacitor is removed, making the loop exceedingly stable and allowing the use of very small ceramic output capacitors. This configuration causes the output voltage to shift by the inductor series resistance multiplied by the load current. This voltagepositioning load regulation greatly reduces overshoot during load transients, which effectively halves the peak-to-peak output-voltage excursions compared to traditional step-down converters. Dynamic Voltage Scaling (DVS) Control with Ramp Rate The step-down output voltage has a variable ramp rate that is set by the BUCKRAMP bits in the DVS RAMP CONTROL register. This register controls the outputvoltage ramp rate during a positive voltage change (for example, from 1.0V to 1.1V), and a negative voltage change (for example, from 1.1V to 1.0V). Ramp rate adjustment range is from 1mV/Fs to 12mV/Fs in the step of 1mV/Fs. After the step-down converter is in regulation, its output voltage can dynamically ramp up at the rate set by the BUCKRAMP bits for a positive voltage change. For a negative voltage change, the decay rate of the output voltage depends on the size of the external load: a small load results in an output-voltage decay that is slower than the specified ramp rate and LX sinks current from the output capacitor to actively ramp down the output voltage; a large load (greater than COUT x Ramp Rate) results in an output-voltage decay with the specified ramp rate. When the step-down converter is disabled, the output voltage decays to ground at a rate determined by the output capacitance, internal discharge resistance, and the external load.
The MAX8893A/MAX8893B/MAX8893C step-down converter is optimized for high-efficiency voltage conversion over a wide load range, while maintaining excellent transient response, minimizing external component size, and output voltage ripple. The step-down converter also features an optimized on-resistance internal MOSFET switch and synchronous rectifier to maximize efficiency. The IC utilizes a proprietary hysteretic-PWM control scheme that switches with nearly fixed frequency up to 4MHz allowing for ultra-small external components. Its output current is guaranteed up to 500mA. When the step-down output voltage falls below the regulation threshold, the error comparator begins a switching cycle by turning on the high-side switch. This switch remains on until the minimum on-time (tON) expires and the output voltage is in regulation or the current-limit threshold is exceeded. Once off, the high-side switch
Step-Down DC-DC Converter Control Scheme
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
The MAX8893A/MAX8893B/MAX8893C contain five lowdropout, low-quiescent-current, high-accuracy, linear regulators (LDOs). The LDO output voltages are set through the I2C serial interface. The LDOs include an internal reference, error amplifier, p-channel pass transistor, and internal programmable voltage-divider. Each error amplifier compares the reference voltage to a feedback voltage and amplifies the difference. If the feedback voltage is lower than the reference voltage, the pass-transistor gate is pulled lower, allowing more current to pass to the output and increasing the output voltage. If the feedback voltage is too high, the passtransistor gate is pulled up, allowing less current to pass to the output. The default regulator output voltages are set as shown in Table 1. All regulator output voltages (BUCK, LDO1, LDO2, LDO3, LDO4, and LDO5) are programmable through the I2C serial interface.
Low-Dropout Linear Regulators
The MAX8893A/MAX8893B/MAX8893C have individual enable inputs for each regulator, load switch, and USB switch. The individual enable inputs (ENBUCK, ENLDO1, ENLDO2, ENLDO3, ENLDO45, ENLS) are logically ORed with the corresponding I2C serial interface control bit. ENUSB input is logically NANDed with the EUSB bit. See Tables 2, 3, and 4 for enable logic truth tables. The enable inputs (ENBUCK, ENLDO_, and ENLS) are internally pulled to AGND by an 800kI (typ) pulldown resistor. ENUSB is internally pulled up to BATT by an 800k (typ) pullup resistor. Any valid enable input signal turns on the MAX8893A/ MAX8893B/MAX8893C. After the IC is up, the I2C interface is active and the IC can be reprogrammed through the I2C interface. To turn off the IC, both I2C bus and enable inputs must be low. All I2C register values return to the default value when no enable input signals are present.
Enable Inputs (ENBUCK, ENLDO_, ENLS, ENUSB)
MAX8893A/MAX8893B/MAX8893C
Default Regulator Output Voltages
Table 1. Default Regulator Output Voltages
PART MAX8893A MAX8893B MAX8893C BUCK (V) 1.0 1.0 1.0 LDO1 (V) 2.8 2.6 1.8 LDO2 (V) 2.6 2.6 2.6 LDO3 (V) 3.3 3.3 3.3 LDO4 (V) 3.0 3.3 3.3 LDO5 (V) 1.0 2.8 3.0
Table 2. Truth Table for BUCK, LDO1 to LDO3, and Load Switch
ENABLE INPUT (ENBUCK, ENLDO1, ENLDO2, ENLDO3, OR ENLS) 0 0 1 1 CORRESPONDING I2C ON/OFF CONTROL BIT 0 1 0 1 CORRESPONDING REGULATOR OR SWITCH Off On On On
Table 3. Truth Table for LDO4 and LDO5
ENABLE INPUT (ENLDO45) 0 0 0 0 1 1 ELDO4 BIT 0 0 1 1 0 1 ELDO5 BIT 0 1 0 1 0 1 LDO4 Off Off On On On On LDO5 Off On Off On On On
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
Table 4. Truth Table for USB Switch
ENUSB 0 0 1 1 EUSB BIT 0 1 0 1 USB SWITCH On On On Off
Drive ENBUCK or ENLDO_ high to turn on the BUCK converter or the corresponding LDOs. When ENBUCK and ENLDO_ are connected together and driven from low to high, all the regulators are turned on with the preset power-up sequencing. There are time delays between each regulator to limit input current rush. The MAX8893A/MAX8893B/MAX8893C have different power-up time delays between each regulator. See the Typical Operating Characteristics for details. When VIN rises above the undervoltage lockout threshold (2.85V typ), the MAX8893A/MAX8893B/MAX8893C can be enabled by driving any EN_ high or ENUSB low. The UVLO threshold hysteresis is typically 0.5V. Therefore, if VIN falls below 2.35V (typ), the undervoltage lockout circuitry disables all outputs and all internal registers are reset to default values. Bypass REFBP to AGND with a 0.1FF ceramic capacitor to reduce noise on the LDO outputs. REFBP is high impedance in shutdown.
Power-Up Sequencing
The USB high-speed switch is a Q15kV ESD-protected DPDT analog switch. It is ideal for USB 2.0 Hi-Speed (480Mbps) switching applications and also meets USB low- and full-speed requirements. The USB switch is fully specified to operate from a single 2.7V to 5.5V supply. The switch is based on charge-pumpassisted n-channel architecture. The switch also features a shutdown mode to reduce the quiescent current. Digital Control Input The USB high-speed switch provides a single-bit control logic input, CB. CB controls the position of the switches as shown in Figure 7. Driving CB rail-to-rail minimizes power consumption.
BATT ENUSB
USB High-Speed Switch
Undervoltage Lockout
Reference Noise Bypass (REFBP)
CB
MAX8893A MAX8893B MAX8893C
NC1 COM1 NO1
Thermal-overload protection limits total power dissipation in the MAX8893A/MAX8893B/MAX8893C. The step-down converter and LDOs have independent thermal protection circuits. When the junction temperature exceeds +160NC, the LDO, or step-down thermaloverload protection circuitry disables the corresponding regulators, allowing the IC to cool. The LDO thermaloverload protection circuit enables the LDOs after the LDO junction temperature cools down, resulting in pulsed LDO outputs during continuous thermal-overload conditions. The step-down converter's thermal-overload protection circuitry enables the step-down converter after the junction temperature cools down. Thermaloverload protection safeguards the IC in the event of fault conditions.
Thermal-Overload Protection
NC2 COM2 NO2
ENUSB 0 0 1
CB 0 1 X
N0_ OFF ON OFF
NC_ ON OFF OFF
COM_ -- -- HI-Z
X = DON'T CARE.
Figure 7. USB Switch Functional Diagram/Truth Table
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
Analog Signal Levels The on-resistance of the USB switch is very low and stable as the analog input signals are swept from ground to VIN (see the Typical Operating Characteristics). These switches are bidirectional, allowing NO_, NC_, and COM_ to be configured as either inputs or outputs. The charge-pump-assisted n-channel architecture allows the switch to pass analog signals that exceed VIN up to the overvoltage fault protection threshold. This allows USB signals that exceed VIN to pass, allowing compliance with USB requirements for voltage levels. Overvoltage Fault Protection The USB switch features overvoltage fault protection on COM_. Fault protection protects the switch and USB transceiver from damaging voltage levels. When voltages on COM_ exceed the fault protection threshold (VFP), COM_, NC_, and NO_ are high impedance. Enable Input (ENUSB) The USB switch features a shutdown mode that reduces the quiescent current supply and places COM_ in high impedance. Drive ENUSB high to place the USB switch in shutdown mode. Drive ENUSB low to allow the USB switch to enter normal operation. The MAX8893A/MAX8893B/MAX8893C include an ultralow RON p-channel MOSFET load switch. The switch has its own enable input, ENLS. When it is enabled, its output soft-starts with I2C programmed rising time to avoid inrush current. See Table 8. The switch input is from the step-down converter output and can operate over the 0.8V to 2.4V range. With LS_ADEN bit set to 1, when the switch is disabled, an internal 100 resistor is connected between the load switch output and ground for quick discharging. An I2C-compatible, 2-wire serial interface controls all the regulator output voltages, load switch timing, individual enable/disable control, and other parameters. The serial bus consists of a bidirectional serial-data line (SDA) and a serial-clock input (SCL). The MAX8893A/MAX8893B/ MAX8893C are slave-only devices, relying upon a master to generate a clock signal. The master initiates data transfer to and from the MAX8893A/MAX8893B/ MAX8893C and generates SCL to synchronize the data transfer (Figure 8). I2C is an open-drain bus. Both SDA and SCL are bidirectional lines, connected to a positive supply voltage through a pullup resistor. They both have Schmitt triggers and filter circuits to suppress noise spikes on the bus to assure proper device operation.
Load Switch
MAX8893A/MAX8893B/MAX8893C
I2C Serial Interface
SDA tSU,DAT tHD,DAT tHIGH tSU,STA tBUF tHD,STA tSU,STO
tLOW SCL tHD,STA
tR
tF REPEATED START CONDITION STOP CONDITION START CONDITION
START CONDITION
Figure 8. 2-Wire Serial Interface Timing Detail
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
Slave Address A bus master initiates communication with a slave device (MAX8893A/MAX8893B/MAX8893C) by issuing a START condition followed by the slave address. The slave address byte consists of 7 address bits (0111110) and a read/write bit (RW). Its address is 0x7C for write operations and 0x7D for read operations. After receiving the proper address, the MAX8893A/MAX8893B/ MAX8893C issue an acknowledge by pulling SDA low during the ninth clock cycle. Bit Transfer Each data bit, from the most significant bit to the least significant bit, is transferred one by one during each clock cycle. During data transfer, the SDA signal is allowed to change only during the low period of the SCL clock and it must remain stable during the high period of the SCL clock (Figure 9). START and STOP Conditions Both SCL and SDA remain high when the bus is not busy. The master signals the beginning of a transmission with a START (S) condition by transitioning SDA from high to low while SCL is high. When the master has finished communicating with the MAX8893A/MAX8893B/MAX8893C, it issues a STOP (P) condition by transitioning SDA from low to high while SCL is high. The bus is then free for another transmission (Figure 10). Both START and STOP conditions are generated by the bus master.
SCL
SDA
START CONDITION (S)
DATA LINE STABLE DATA VALID
DATA ALLOWED TO CHANGE
STOP CONDITION (P)
Figure 9. Bit Transfer
SDA
SCL
START CONDITION
STOP CONDITION
Figure 10. START and STOP Conditions 32 _____________________________________________________________________________________
PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
Acknowledge The acknowledge bit is used by the recipient to handshake the receipt of each byte of data (Figure 11). After data transfer, the master generates the acknowledge clock pulse and the recipient pulls down the SDA line during this acknowledge clock pulse, such that the SDA line stays low during the high duration of the clock pulse. When the master transmits the data to the MAX8893A/ MAX8893B/MAX8893C, it releases the SDA line and the MAX8893A/MAX8893B/MAX8893C take the control of the SDA line and generate the acknowledge bit. When SDA remains high during this 9th clock pulse, this is defined as the not acknowledge signal. The master can then generate either a STOP condition to abort the transfer, or a REPEATED START condition to start a new transfer. Write Operation The MAX8893A/MAX8893B/MAX8893C recognize the write-byte protocol as defined in the SMBusTM specification and shown in section A of Figure 12. The write-byte protocol allows the I2C master device to send 1 byte of data to the slave device. The write-byte protocol requires a register pointer address for the subsequent write. The MAX8893A/MAX8893B/MAX8893C acknowledge any register pointer even though only a subset of those registers actually exists in the device. The write-byte protocol is as follows: 1) The master sends a start command. 2) The master sends the 7-bit slave address followed by a write bit (0x7C). 3) The addressed slave asserts an acknowledge by pulling SDA low. 4) The master sends an 8-bit register pointer. 5) The slave acknowledges the register pointer. 6) The master sends a data byte. 7) The slave updates with the new data. 8) The slave acknowledges the data byte. 9) The master sends a STOP condition. In addition to the write-byte protocol, the MAX8893A/ MAX8893B/MAX8893C can write to multiple registers as
MAX8893A/MAX8893B/MAX8893C
SDA BY MASTER D7 D6 D0
NOT ACKNOWLEDGE SDA BY SLAVE
SCL 1 2
ACKNOWLEDGE 8 9
START CONDITION
CLOCK PULSE FOR ACKNOWLEDGEMENT
Figure 11. Acknowledge
shown in section B of Figure 12. This protocol allows the I2C master device to address the slave only once and then send data to a sequential block of registers starting at the specified register pointer. Use the following procedure to write to a sequential block of registers: 1) 2) 3) 4) 5) 6) 7) 8) 9) The master sends a start command. The master sends the 7-bit slave address followed by a write bit (0x7C). The addressed slave asserts an acknowledge by pulling SDA low. The master sends the 8-bit register pointer of the first register to write. The slave acknowledges the register pointer. The master sends a data byte. The slave updates with the new data. The slave acknowledges the data byte. Steps 6 to 8 are repeated for as many registers in the block, with the register pointer automatically incremented each time.
10) The master sends a STOP condition.
SMBus is a trademark of Intel Corp.
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FPMIC for Multimedia Application Processor in 2.5mm x 3.0mm WLP MAX8893A/MAX8893B/MAX8893C
LEGEND MASTER TO SLAVE SLAVE TO MASTER
A. WRITING TO A SINGLE REGISTER WITH THE WRITE BYTE PROTOCOL 1 S 7 SLAVE ADDRESS R/W 1 0 1 A 8 REGISTER POINTER 1 A 8 DATA 1 A 1 P NUMBER OF BITS
B. WRITING TO MULTIPLE REGISTERS 1 S 7 SLAVE ADDRESS R/W 8 DATA X+n-1 1 A 8 DATA X+n 1 AP 1 0 1 A 8 REGISTER POINTER X 1 A 8 DATA X 1 A 8 DATA X+1 NUMBER OF BITS 1 A NUMBER OF BITS
Figure 12. Writing to the MAX8893A/MAX8893B/MAX8893C
Read Operation The method for reading a single register (byte) is shown in section A of Figure 13. To read a single register: 1) 2) 3) 4) 5) 6) 7) 8) 9) The master sends a start command. The master sends the 7-bit slave address followed by a read bit (0x7D). The addressed slave asserts an acknowledge by pulling SDA low. The master sends an 8-bit register pointer. The slave acknowledges the register pointer. The master sends a REPEATED START condition. The master sends the 7-bit slave address followed by a read bit. The slave asserts an acknowledge by pulling SDA low. The slave sends the 8-bit data (contents of the register).
section B of Figure 13. Use the following procedure to read a sequential block of registers: 1) 2) 3) 4) 5) 6) 7) 8) 9) The master sends a start command. The master sends the 7-bit slave address followed by a read bit (0x7D). The addressed slave asserts an acknowledge by pulling SDA low. The master sends an 8-bit register pointer of the first register in the block. The slave acknowledges the register pointer. The master sends a REPEATED START condition. The master sends the 7-bit slave address followed by a read bit. The slave asserts an acknowledge by pulling SDA low. The slave sends the 8-bit data (contents of the register).
10) The master asserts an acknowledge by pulling SDA low. 11) The master sends a STOP condition. In addition, the MAX8893A/MAX8893B/MAX8893C can read a block of multiple sequential registers as shown in
10) The master asserts an acknowledge by pulling SDA low. 11) Steps 9 and 10 are repeated for as many registers in the block, with the register pointer automatically incremented each time. 12) The master sends a STOP condition.
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
LEGEND MASTER TO SLAVE SLAVE TO MASTER A. READING A SINGLE REGISTER 1 S 7 SLAVE ADDRESS R/W 1 0 1 A 8 REGISTER POINTER 1 1 8 SLAVE ADDRESS 1 1 1 A 8 DATA 1 A 1 P NUMBER OF BITS
A Sr
B. READING MULTIPLE REGISTERS 1 S 7 SLAVE ADDRESS R/W 8 DATA X+1 1 A ... 8 DATA X+n-1 1 0 1 A 8 REGISTER POINTER X 1 A 1 Sr 8 SLAVE ADDRESS R/W 1 A 8 DATA X+n 1 1 NUMBER OF BITS 11 1 A 8 DATA X 1 A NUMBER OF BITS
AP
Figure 13. Reading from the MAX8893A/MAX8893B/MAX8893C
Table 5. Register Map
NAME TABLE REGISTER ADDRESS (hex) 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 RESET VALUE 0x01 0xFF 0x08 0x09 0x02 0x0C 0x0A 0x02 0x0E 0x11 0x16 0x19 0x02 0x14 0x16 N/A TYPE DESCRIPTION BUCK, LDO1-LDO5, load switch, and USB switch ON/OFF control Active discharge enable/disable control for step-down converter and LDO regulators Load switch rising time, turn-on, and turnoff delay time control BUCK enable and ramp rate control BUCK output voltage setting LDO1 output voltage setting LDO2 output voltage setting LDO3 output voltage setting LDO4 output voltage setting
ON/OFF CONTROL ACTIVE DISCHARGE CONTROL LS TIME CONTROL DVS RAMP CONTROL BUCK LDO1 LDO2 LDO3 LDO4
Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14
R/W R/W R/W R/W R/W R/W R/W R/W R/W
LDO5 SVER
Table 15 Table 16
0x09 0x46
R/W R only
LDO5 output voltage setting Die type information
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
Table 6. On/Off Control
This register contains BUCK, LDO1-LDO5, USB switch, and load switch ON/OFF controls.
REGISTER NAME Register Pointer Reset Value Type Special Features BIT B7 (MSB) B6 B5 B4 B3 B2 B1 B0 (LSB) NAME EBUCK ELS ELDO1 ELDO2 ELDO3 ELDO4 ELDO5 EUSB DESCRIPTION 0 = BUCK is disabled 1 = BUCK is enabled 0 = Load switch is disabled 1 = Load switch is enabled 0 = LDO1 is disabled 1 = LDO1 is enabled 0 = LDO2 is disabled 1 = LDO2 is enabled 0 = LDO3 is disabled 1 = LDO3 is enabled 0 = LDO4 is disabled 1 = LDO4 is enabled 0 = LDO5 is disabled 1 = LDO5 is enabled 0 = USB switch is enabled 1 = USB switch is disabled ON/OFF CONTROL 0x00 0x01 Read/write -- DEFAULT VALUE 0 0 0 0 0 0 0 1
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
Table 7. Active Discharge Control
This register contains the active discharge enable bits for the BUCK, load switch, and LDO1-LDO5.
REGISTER NAME Register Pointer Reset Value Type Special Features BIT B7 (MSB) B6 B5 B4 B3 B2 B1 B0 (LSB) NAME BUCK_ADEN LS_ADEN LDO1_ADEN LDO2_ADEN LDO3_ADEN LDO4_ADEN LDO5_ADEN -- DESCRIPTION 0 = BUCK active discharge is disabled 1 = BUCK active discharge is enabled 0 = Load switch active discharge is disabled 1 = Load switch active discharge is enabled 0 = LDO1 active discharge is disabled 1 = LDO1 active discharge is enabled 0 = LDO2 active discharge is disabled 1 = LDO2 active discharge is enabled 0 = LDO3 active discharge is disabled 1 = LDO3 active discharge is enabled 0 = LDO4 active discharge is disabled 1 = LDO4 active discharge is enabled 0 = LDO5 active discharge is disabled 1 = LDO5 active discharge is enabled Reserved for future use ACTIVE DISCHARGE CONTROL 0x01 0xFF Read/write -- DEFAULT VALUE 1 1 1 1 1 1 1 --
MAX8893A/MAX8893B/MAX8893C
37
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FPMIC for Multimedia Application Processor in 2.5mm x 3.0mm WLP MAX8893A/MAX8893B/MAX8893C
Table 8. LS Time Control
This register contains the load switch timing controls.
REGISTER NAME Register Pointer Reset Value Type Special Features BIT B7 (MSB) B6 B5 B4 LSRT B3 NAME -- -- -- DESCRIPTION Reserved for future use Reserved for future use Reserved for future use Load switch rising time control 00 = 10Fs 01 = 27Fs 10 = 100Fs 11 = 300Fs Load switch turn-on delay time control 0 = Load switch turn-on delay OFF 1 = Load switch turn-on delay is 34Fs Load switch turn-off delay time control 00 = 11Fs 01 = 63Fs 10 = 177Fs 11 = 11Fs LS TIME CONTROL 0x02 0x08 Read/write -- DEFAULT VALUE -- -- --
01
B2
LSTOD
0
B1 LSTOFFD B0 (LSB)
00
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
Table 9. DVS Ramp Control
This register contains DVS enable/disable and ramp rate control for the step-down converter.
REGISTER NAME Register Pointer Reset Value Type Special Features BIT B7 (MSB) B6 B5 B4 NAME -- -- -- ENDVS DESCRIPTION Reserved for future use Reserved for future use Reserved for future use 0 = BUCK DVS is disabled 1 = BUCK DVS is enabled Step-down output voltage ramp rate control 0000 (0x0) = 1mV/Fs 0001 (0x1) = 2mV/Fs 0010 (0x2) = 3mV/Fs 0011 (0x3) = 4mV/Fs 0100 (0x4) = 5mV/Fs 0101 (0x5) = 6mV/Fs 0110 (0x6) = 7mV/Fs 0111 (0x7) = 8mV/Fs 1000 (0x8) = 9mV/Fs 1001 (0x9) = 10mV/Fs 1010 (0xA) = 11mV/Fs 1011 (0xB) = 12mV/Fs DVS RAMP CONTROL 0x03 0x09 Read/write -- DEFAULT VALUE -- -- -- 0
MAX8893A/MAX8893B/MAX8893C
B3
B2 BUCKRAMP B1
1001 (0x9)
B0 (LSB)
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FPMIC for Multimedia Application Processor in 2.5mm x 3.0mm WLP MAX8893A/MAX8893B/MAX8893C
Table 10. Buck
This register contains the step-down converter output voltage controls.
REGISTER NAME Register Pointer Reset Value Type Special Features BUCK 0x04 0x02 Read/write --
BIT B7 (MSB) B6 B5 B4
NAME
DESCRIPTION 00000000 (0x00) = 0.8V 00000001 (0x01) = 0.9V 00000010 (0x02) = 1.0V 00000011 (0x03) = 1.1V 00000100 (0x04) = 1.2V 00000101 (0x05) = 1.3V 00000110 (0x06) = 1.4V 00000111 (0x07) = 1.5V 00001000 (0x08) = 1.6V 00001001 (0x09) = 1.7V 00001010 (0x0A) = 1.8V 00001011 (0x0B) = 1.9V 00001100 (0x0C) = 2.0V 00001101 (0x0D) = 2.1V 00001110 (0x0E) = 2.2V 00001111 (0x0F) = 2.3V 00010000 (0x10) = 2.4V
DEFAULT VALUE
BUCK B3 B2 B1 B0 (LSB)
00000010 (0x02)
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
Table 11. LDO1
This register contains LDO1 output voltage controls.
REGISTER NAME Register Pointer Reset Value Type Special Features BIT B7 (MSB) B6 B5 B4 LDO1 B3 B2 B1 B0 (LSB) NAME DESCRIPTION 00000000 (0x00) = 1.6V 00000001 (0x01) = 1.7V 00000010 (0x02) = 1.8V 00000011 (0x03) = 1.9V 00000100 (0x04) = 2.0V 00000101 (0x05) = 2.1V 00000110 (0x06) = 2.2V 00000111 (0x07) = 2.3V 00001000 (0x08) = 2.4V 00001001 (0x09) = 2.5V 00001010 (0x0A) = 2.6V 00001011 (0x0B) = 2.7V 00001100 (0x0C) = 2.8V 00001101 (0x0D) = 2.9V 00001110 (0x0E) = 3.0V 00001111 (0x0F) = 3.1V 00010000 (0x10) = 3.2V 00010001 (0x11) = 3.3V ON/OFF CONTROL 0x05 0x0C (MAX8893A) 0x0A (MAX8893B) 0x02 (MAX8893C) Read/write -- DEFAULT VALUE
MAX8893A/MAX8893B/MAX8893C
41
MAX8893A 00001100 (0x0C) MAX8893B 00001010 (0x0A) MAX8893C 00000010 (0x02)
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FPMIC for Multimedia Application Processor in 2.5mm x 3.0mm WLP MAX8893A/MAX8893B/MAX8893C
Table 12. LDO2
This register contains LDO2 output voltage controls.
REGISTER NAME Register Pointer Reset Value Type Special Features BIT B7 (MSB) B6 B5 B4 B3 B2 B1 NAME DESCRIPTION 00000000 (0x00) = 1.2V 00000001 (0x01) = 1.3V 00000010 (0x02) = 1.4V 00000011 (0x03) = 1.5V 00000100 (0x04) = 1.6V 00000101 (0x05) = 1.7V 00000110 (0x06) = 1.8V 00000111 (0x07) = 1.9V 00001000 (0x08) = 2.0V 00001001 (0x09) = 2.1V 00001010 (0x0A) = 2.2V 00001011 (0x0B) = 2.3V 00001100 (0x0C) = 2.4V 00001101 (0x0D) = 2.5V 00001110 (0x0E) = 2.6V 00001111 (0x0F) = 2.7V 00010000 (0x10) = 2.8V 00010001 (0x11) = 2.9V 00010010 (0x12) = 3.0V 00010011 (0x13) = 3.1V 00010100 (0x14) = 3.2V 00010101 (0x15) = 3.3V LDO2 0x06 0x0E Read/write -- DEFAULT VALUE
LDO2
00001110 (0x0E)
B0 (LSB)
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
Table 13. LDO3
This register contains LDO3 output voltage controls.
REGISTER NAME Register Pointer Reset Value Type Special Features LDO3 0x07 0x11 Read/write --
MAX8893A/MAX8893B/MAX8893C
BIT B7 (MSB) B6 B5 B4
NAME
DESCRIPTION 00000000 (0x00) = 1.6V 00000001 (0x01) = 1.7V 00000010 (0x02) = 1.8V 00000011 (0x03) = 1.9V 00000100 (0x04) = 2.0V 00000101 (0x05) = 2.1V 00000110 (0x06) = 2.2V 00000111 (0x07) = 2.3V 00001000 (0x08) = 2.4V 00001001 (0x09) = 2.5V 00001010 (0x0A) = 2.6V 00001011 (0x0B) = 2.7V 00001100 (0x0C) = 2.8V 00001101 (0x0D) = 2.9V 00001110 (0x0E) = 3.0V 00001111 (0x0F) = 3.1V 00010000 (0x10) = 3.2V 00010001 (0x11) = 3.3V
DEFAULT VALUE
LDO3 B3 B2 B1 B0 (LSB)
00010001 (0x11)
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
Table 14. LDO4
This register contains LDO4 output voltage controls.
REGISTER NAME Register Pointer Reset Value Type Special Features BIT B7 (MSB) NAME DESCRIPTION 00000000 (0x00) = 0.8V 00000001 (0x01) = 0.9V 00000010 (0x02) = 1.0V 00000011 (0x03) = 1.1V 00000100 (0x04) = 1.2V 00000101 (0x05) = 1.3V 00000110 (0x06) = 1.4V 00000111 (0x07) = 1.5V 00001000 (0x08) = 1.6V 00001001 (0x09) = 1.7V 00001010 (0x0A) = 1.8V 00001011 (0x0B) = 1.9V 00001100 (0x0C) = 2.0V 00001101 (0x0D) = 2.1V 00001110 (0x0E) = 2.2V 00001111 (0x0F) = 2.3V 00010000 (0x10) = 2.4V 00010001 (0x11) = 2.5V 00010010 (0x12) = 2.6V 00010011 (0x13) = 2.7V 00010100 (0x14) = 2.8V 00010101 (0x15) = 2.9V 00010110 (0x16) = 3.0V 00010111 (0x17) = 3.1V 00011000 (0x18) = 3.2V 00011001 (0x19) = 3.3V LDO4 0x08 0x16(MAX8893A) 0x19(MAX8893B/MAX8893C) Read/write -- DEFAULT VALUE
B6
B5
B4 LDO4 B3
MAX8893A 00010110 (0x16) MAX8893B /MAX8893C 00011001 (0x19)
B2
B1
B0 (LSB)
44
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
Table 15. LDO5
This register contains LDO5 output voltage controls.
REGISTER NAME Register Pointer Reset Value Type Special Features BIT B7 (MSB) NAME DESCRIPTION 00000000 (0x00) = 0.8V 00000001 (0x01) = 0.9V 00000010 (0x02) = 1.0V 00000011 (0x03) = 1.1V 00000100 (0x04) = 1.2V 00000101 (0x05) = 1.3V 00000110 (0x06) = 1.4V 00000111 (0x07) = 1.5V 00001000 (0x08) = 1.6V 00001001 (0x09) = 1.7V 00001010 (0x0A) = 1.8V 00001011 (0x0B) = 1.9V 00001100 (0x0C) = 2.0V 00001101 (0x0D) = 2.1V 00001110 (0x0E) = 2.2V 00001111 (0x0F) = 2.3V 00010000 (0x10) = 2.4V 00010001 (0x11) = 2.5V 00010010 (0x12) = 2.6V 00010011 (0x13) = 2.7V 00010100 (0x14) = 2.8V 00010101 (0x15) = 2.9V 00010110 (0x16) = 3.0V 00010111 (0x17) = 3.1V 00011000 (0x18) = 3.2V 00011001 (0x19) = 3.3V LDO5 0x09 0x02 (MAX8893A) 0x14 (MAX8893B) 0x16 (MAX8893C) Read/write -- DEFAULT VALUE
MAX8893A/MAX8893B/MAX8893C
B6
B5
B4 LDO5 B3
MAX8893A 00000010 (0x02) MAX8893B 00010100 (0x14) MAX8893C 00010110 (0x16)
B2
B1
B0 (LSB)
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FPMIC for Multimedia Application Processor in 2.5mm x 3.0mm WLP MAX8893A/MAX8893B/MAX8893C
Table 16. SVER
This register contains the MAX8893A/MAX8893B/MAX8893C version number.
REGISTER NAME Register Pointer Reset Value Type Special Features BIT B7 (MSB) B6 B5 B4 B3 B2 B1 SVER B0 (LSB) NAME -- -- -- -- -- -- DESCRIPTION Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use Reserved for future use 00 = MAX8893A 01 = MAX8893B 10 = MAX8893C SVER 0x46 N/A Read -- DEFAULT VALUE -- -- -- -- -- -- --
Applications Information
Step-Down Converter
Input Capacitor The input capacitor, CIN1, reduces the current peaks drawn from the battery or input power source and reduces switching noise in the IC. The impedance of CIN1 at the switching frequency should be kept very low. Ceramic capacitors with X5R or X7R temperature characteristics are highly recommended due to their small size, low ESR, and small temperature coefficients. Due to the step-down converter's fast soft-start, the input capacitance can be very low. For most applications, a 2.2FF capacitor is sufficient. Connect CIN1 as close as possible to the IC to minimize the impact of PCB trace inductance. For other input capacitors, use a 2.2FF ceramic capacitor from IN2 to ground and a 2.2FF ceramic capacitor from BATT to ground. Output Capacitor The output capacitor, CBUCK, is required to keep the output voltage ripple small and to ensure regulation loop stability. CBUCK must have low impedance at the switching frequency. Ceramic capacitors with X5R or X7R temperature characteristics are highly recommended due to their small size, low ESR, and small temperature coefficients. Due to the unique feedback network, the
output capacitance can be very low. For most applications a 2.2FF capacitor is sufficient. For optimum loadtransient performance and very low output ripple, the output capacitor value in FF should be equal to or larger than the inductor value in FH. Inductor Selection The recommended inductor for the step-down converter is from 1.0FH and 4.7FH. Low inductance values are physically smaller, but require faster switching, resulting in some efficiency loss. The inductor's DC current rating needs to be only 100mA greater than the application's maximum load current because the step-down converter features zero current overshoot during startup and load transients. For output voltages above 2.0V, when light load efficiency is important, the minimum recommended inductor is 2.2FH. For optimum voltage-positioning load transients, choose an inductor with DC series resistance in the 50m to 150m range. To achieve higher efficiency at heavy loads (above 200mA) or minimum load regulation (but some transient overshoot), the inductor resistance should be kept below 100m. For light -oad applications up to 200mA, much higher resistance is acceptable with very little impact on performance. See Table 17 for some suggested inductors.
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
Table 17. Suggested Inductors
MANUFACTURER SERIES INDUCTANCE (FH) 1.0 2.2 1.0 1.5 2.2 3.3 1.0 1.5 2.2 3.3 1.0 1.5 2.2 3.3 4.7 1.0 2.2 4.7 2.2 4.7 1.5 2.2 3.3 1.5 2.2 2.7 3.3 1.5 2.2 3.3 4.7 ESR (mI) 150 230 90 110 130 200 60 70 90 110 80 110 130 160 200 60 100 150 100 170 130 170 190 100 120 150 170 50 80 100 140 ISAT (mA) 300 240 455 350 315 280 500 400 340 270 775 660 600 500 430 1000 790 650 400 300 1230 1080 1010 1290 1140 980 900 900 780 600 500 DIMENSIONS (LTYP O WTYP O HMAX) (mm) 2.0 x 1.25 x 1.45
MAX8893A/MAX8893B/MAX8893C
LB2012
LB2016
2.0 x 1.6 x 1.8
Taiyo Yuden
LB2518
2.5 x 1.8 x 2.0
LBC2518
2.5 x 1.8 x 2.0
LQH32C_53 Murata LQM43FN
3.2 x 2.5 x 1.7
4.5 x 3.2 x 0.9
D310F TOKO D312C
3.6 x 3.6 x 1.0
3.6 x 3.6 x 1.2
Sumida
CDRH2D11
3.2 x 3.2 x 1.2
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FPMIC for Multimedia Application Processor in 2.5mm x 3.0mm WLP MAX8893A/MAX8893B/MAX8893C
For LDOs, the required output capacitance is dependent on the load currents. With rated maximum load currents, 2.2FF (typ) capacitors are recommended for LDO1, LDO2, LDO3, and LDO5 and a 1.0FF capacitor is recommended for LDO4. For loads less than 150mA, it is sufficient to use 1.0FF capacitors for stable operation over the full temperature range for LDO1, LDO2, LDO3, and LDO5. Reduce output noise and improve load transient response, stability, and power-supply rejection by using larger output capacitors.
Capacitors for LDOs
ASIC I D+ HI-SPEED USB TRANSCEIVER DNC1 NO1 MAX8893A MAX8893B MAX8893C COM1 D+ NC2 ASIC II D+ HI-SPEED USB TRANSCEIVER DGND USB CONNECTOR COM2 NO2 DVBUS
USB High-Speed Switch
USB Switching The USB high-speed switch is fully compliant with the USB 2.0 specification. The low on-resistance and low on-capacitance of these switches make it ideal for highperformance switching applications. It is ideal for routing USB data lines (see Figure 14) and for applications that require switching between multiple USB hosts (see Figure 15). The USB switch also features overvoltage fault protection to guard systems against shorts to the USB VBUS voltage that is required for all USB applications. Extended ESD Protection As with all Maxim devices, ESD-protection structures are incorporated on all pins to protect against electrostatic discharges encountered during handling and assembly. COM1 and COM2 are further protected against static electricity. The state-of-the-art structures are developed to protect these pins against ESD up to 15kV without damage. The ESD structures withstand high ESD in normal operation and when the device is powered down. After an ESD event, the USB switch continues to function without latchup. The USB high-speed switch is characterized for protection to the following limits: U 15kV using Human Body Model U 8kV using IEC 61000-4-2 Contact Discharge method U 15kV using IEC 61000-4-2 Air-Gap Discharge method
Figure 14. USB Data Routing/Typical Application Circuit
MAX8893A MAX8893B MAX8893C
NC1 D+ HI-SPEED USB TRANSCEIVER DCOM2 COM1
D+ USB HOST I
DNO1
NC2 NO2
D+ USB HOST II
D-
Figure 15. Switching Between Multiple USB Hosts
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
High switching frequencies and relatively large peak currents make the PCB layout a very important aspect of design. Good design minimizes excessive EMI on the voltage gradients in the ground plane that can result in instability or regulation errors. Connect the input and output capacitors as close as possible to the IC. Connect the inductor as close as possible to the IC and keep the traces short, direct, and wide. Connect AGND to the exposed pad directly under the IC. Connect AGND and PGND to the ground plane. Keep noisy traces, such as the LX node, as short as possible.
PCB Layout and Routing
USB Hi-Speed requires careful PCB layout with 45 controlled-impedance matched traces of equal lengths. Ensure that bypass capacitors are as close as possible to the IC. Use large ground planes where possible. Refer to the MAX8893 evaluation kit for an example PCB layout design.
MAX8893A/MAX8893B/MAX8893C
Typical Operating Circuit
INPUT 2.7V TO 5.5V 2.2F IN2 2.2F BATT 2.2F LS 1.0F BUCK LX PGND REFBP 0.1F AGND SCL SDA LDO1 2.2F VLDO1 1.6V TO 3.3V VLDO2 1.2V TO 3.3V 2.2F LDO3 2.2F LDO4 1F LDO5 2.2F USB ON/OFF USBSEL ENUSB CB COM1 COM2 NC1 NC2 NO1 NO2 VLDO5 0.8V TO 3.3V VLDO4 0.8V TO 3.3V VLDO3 1.6V TO 3.3V VBUCK 0.8V TO 2.4V 2.2H 2.2F VLS
IN1
I 2C
LS ON/OFF BUCK ON/OFF LDO1 ON/OFF LDO2 ON/OFF LDO3 ON/OFF LDO4/LDO5 ON/OFF
ENLS ENBUCK ENLDO1 ENLDO2 ENLDO3 ENLDO45
MAX8893A MAX8893B MAX8893C
LDO2
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PMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP MAX8893A/MAX8893B/MAX8893C
Chip Information
PROCESS: BiCMOS
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a "+", "#", or "-" in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status.
PACKAGE TYPE 30 WLP PACKAGE CODE W302A3+2 DOCUMENT NO. 21-0016
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FPMICs for Multimedia Application Processors in a 3.0mm x 2.5mm WLP
Revision History
REVISION REVISION NUMBER DATE 0 1 10/09 2/10 Initial release Added new TOCs 53, 54, and 55 to Typical Operating Characteristics section DESCRIPTION PAGES CHANGED -- 21
MAX8893A/MAX8893B/MAX8893C
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
(c)
51
2010 Maxim Integrated Products
Maxim is a registered trademark of Maxim Integrated Products, Inc.

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